Supports simultaneous 1-step and 2-step clock synchronizations on the transmit datapath. When you turn on the Align packet headers to bit boundaries option, the MAC function aligns the IP payload on a bit boundary by adding two bytes to the beginning of Ethernet frames. The following options are NOT available: Bits 1 and 2 are not mutually exclusive. This section discusses the register initialization for the following examples of the Ethernet system using different MAC interfaces with recommended initialization sequences:. At the minimum, you must configure the following functions: You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.

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The user application may want to start reading from the FIFO buffer.

Supports the selection of multiple transceiver channels for dynamic reconfiguration. Set the link timer value from 0 to 16 ms in 8 ns steps MHz clock periods. A magic packet can be a unicast, multicast, or broadcast packet which carries a defined sequence in the payload section.

Turn on this option to export the powerdown signal of the GX transceiver aotera the top-level of your design. The location of the checksum correction field, relative to the first byte of the packet. The values of configuration registers, such as the MAC address and thresholds of the FIFO buffers, are preserved during a software reset. MII in 10M and cut-through mode. Complete triple-speed Ethernet IP: Subsequent channel numbers are in four increments.


Set this clock to the required frequency to get the desired bandwidth on the Avalon-ST transmit interface.

CONFIG_ALTERA_TSE: Altera Triple-Speed Ethernet MAC support

Therefore, turning on this option in multiport Ethernet configurations maximizes alterra use of transceivers within the quad. The number of unwritten entries in the FIFO buffer before the buffer is full. The internal error counter is decremented when four consecutive valid characters are received. The MAC function always accepts broadcast frames. The number received pause frames received.

Triple-Speed Ethernet Intel FPGA IP User Guide

Write one to the most significant bit in the table entry. Data transfers on the MAC Ethernet-side interface are synchronous to the receive and transmit clocks. Asserted when the FIFO buffer reaches the almost-full threshold.

The lower 32 bits of the aOctetsReceivedOK counter. Keep this signal altdra during frame reception, from the first preamble byte until the last byte of the CRC field is received. Assert this signal with the final byte in the frame to indicate that the transmit frame is invalid. Supports configurable register for timestamp correction on both transmit and receive datapaths.

Linux-Kernel Archive: [PATCH] Altera TSE: ALTERA_TSE should depend on HAS_DMA

Enable bit statistics byte counters. The link synchronization state machine acquires link synchronization if the state machine receives three code groups with comma consecutively without error.


The FIFO buffers, which you can configure to 8- or bits wide, store the transmit and receive data. For more information about the statistics counters, refer to Statistics Counters Dword Offset 0x18 — 0x To assign clock signals to use the global clock network.

The MAC function continues to check the frame and payload ste, and asserts the following signals: User applications can use this signal to indicate when to stop writing to the FIFO buffer and initiate backpressure.

Clock Enabler Signal Behavior. All signals on the Avalon-ST receive interface are synchronized on the rising edge of this clock. To ensure the configuration register does linx wait for read timeout when an error occurs, set this bit to 1.

netdev – [PATCH RFC 3/3] Altera TSE: Add Altera Triple Speed Ethernet (TSE) Driver

For more information on the frame length, refer to Length Checking. Static timing adjustment in nanoseconds for outbound timestamps on the receive datapath. The input signals related to the 2-step operation are not important and can be driven low or ignored.

RGMII receive data bus.